This application claims the priority benefit of Taiwan application serial no. 88106503, filed Apr. 23, 1999.
1. Field of the Invention
This invention relates to a computer system using a peripheral component interconnect (PCI) device, and more particularly to PCI bus master and its arbiter with an arbitrating method, in which the PCI master can repeatedly send inquiry signals to a PCI bus after a delay transaction termination is issued on the PCI bus.
2. Description of Related Art
FIG. 1 is a computer system diagram, schematically illustrating a PCI device applied in a computer system. The computer system includes a central processor unit (CPU) 10. which is coupled to a PCI bus 14 through a host bridge 12. Several PCI bus masters, such as a graphic adapter 16a, an expansion bus bridge 16b, a LAN adapter 16c for a use of network, a SCSI host bus adapter 16d for a use for another smaller computer system, and so on are also coupled to the PCI bus. Each PCI bus master can issue a request signal (RST) to use the PCI bus. A bus arbiter in the host bridge 12 then sends a grant signal (GNT) to the PCI bus master to allow the PCI bus master to use the PCI bus 14.
The data communication between PCI compatible devices, such as the PCI bus master or a north bridge of a computer chipset, is typically controlled by an interface control signal, which is described in the following. A cycle frame used to indicate a data access action and its duration is typically generated by an initiator, such as the PCI bus master or the north bridge of the computer chipset. As the cycle frame (FRAME) signal is issued, a data transaction through the PCI bus starts. When the cycle frame signal stays at a low logic level, it means that the transaction is performing. At this stage, during an address phase, an address (AD) bus issues a valid address, and simultaneously sends a valid bus command, which satisfies a PCI format, through a command/byte enable (CBE[3:0]) line so as to instruct the target device to transact data with a data transaction type requested by the initiator. The command/byte enable line includes four bits to have sixteen different commands, each of which has a special purpose and is defined in the PCI bus protocol in detail. After the valid address is issued, the address bus AD sends out the intended data. This period is called a data phase. Simultaneously, immediately after the bus command is issued, a CBE signal with coded commands in the byte is sent out through the CBE line so as to transmit data. As the FRAME signal goes to a high logic level, it means that the last data block of the data transaction is on transmitting status now or the data have been completely transmitted. During read action, an initiator ready (IRDY) signal represents that the initiator is ready for receiving data, and during writing action, a target device ready (TRDY) signal represents that the target device is ready for receiving data. A stop signal is also used to instruct the target device. A STOP signal is used to indicate that the target device requests a stop of data transaction on the initiator.
FIG. 2 is a time waveform sequence, schematically illustrating an operating time sequence during a read action. A bus transaction 20 is defined as a period for use to accomplish a data transaction through the PCI bus. The bus transaction 20 further includes an address phase 22, and several data phases, such as data phases 24a, 24b, and 24c. Each data phase further includes a wait cycle and a data transfer cycle. For example, the data phase 24a/b/c respectively includes a wait cycle 26a/b/c and a data transfer cycle 28a/b/c. Referring to FIG. 2, one can see a read action through the PCI system with related signals described before.
During the first cycle T1 of a clock (CLK), the initiator issues a FRAME signal to start a data transaction. The AD buss sends a start address so as to select a desired target device, and simultaneously send a byte enable command through the CBE line. This byte enable command remains during all data phases 24a, 24b, and 24c. During the second cycle T2, the initiator sends a IRDY signal to indicate the initiator is ready for receiving data. At this moment, the target device is not ready yet so that the wait cycle 26a is needed in the data phase 24a. The initiator stays at a waiting status during the second cycle T2. During the third cycle T3, the target device is ready and sends a TRDY signal to indicate its status. The data phrase 24a turns to the data transfer cycle 28a from the wait cycle 26a. The initiator reads data from the target device in the data transfer cycle 28a, which extends to a fourth cycle T4. During the fourth cycle T4, as data is completely read, the target device changes the status of the TRDY and prepares the second data block. At this moment, the data phase 24b starts and stays at the wait cycle 26b. During a fifth cycle T5, the target device sends the TRDY signal again to start a read of the second data block. The initiator read the second data block during the data transfer cycle 28b. In case that the initiator cannot read the second data block in time, the initiator send an unready IRDY signal at a sixth cycle T6. In this situation, since the TRDY still stays at ready status, the wait cycle 26c of the data phase 24c is caused by the initiator. During a cycle T7, the initiator may be ready again and read the second data block again. The second read block is completely read during a cycle T8. Since the FRAME signal has indicated the second data block is the last data block to be ready. The read action stops at the cycle T8. Both the IRDY and the TRDY change to unready status. Accordingly, the CBE signal and the AD signal are off.
In this conventional action, only one PCI bus master can use the PCI bus at a bus transaction. So, before performing one of functional devices of a multi-function master, the master should receive a use privilege to use the PCI bus. However, in some simple system, the multiple-function master does not release its use privilege after the data transaction finishes.
FIG. 3 is a system block diagram, schematically illustrating a conventional multi-function master, which is compatible with the PCI bus. FIG. 4 is a time sequence, schematically illustrating a conventional arbitrating method used by the conventional multi-function master of FIG. 3 to transmit data.
In FIG. 3, there is a PCI bus 40. A multi-function master 30 is coupled to the PCI bus 40. The multi-function master 30 includes an arbiter 32 and several functional circuits 34, 36, and 38, in which the arbiter 32 is different from the bus arbiter 31. The bus arbiter 31 is used to arbitrate all PCI masters (some are not shown) coupled to the PCI bus 40 so as to provide a use privilege to one of the PCI masters. The arbiter 32 is used to arbitrate which one of the functional circuits 34, 36, and 38 has a privilege to use the multi-function master 30. For example, as the multi-function master 30 obtain its use privilege authorized by the arbiter 31, one of the functional circuits 34, 36, and 38 also needs an authorization from the arbiter 32 so as to used the PCI bus 40.
Some of the functional circuits can be coupled to peripheral apparatus. For example, the functional circuits 34 and 36 are also respectively coupled to a peripheral apparatus 33 and a peripheral apparatus 35. The functional circuits 34 and 36 include, for example, various interface control circuits, such as a communication interface, a simple I/O interface to match the peripheral apparatuses 33 and 35. The functional circuit 38 is built in the multi-function master 30 to independently perform its special function, such as a digital signal processor (DSP). Moreover, a peripheral apparatus 42 can also coupled to the arbiter 32 to directly communicate with the arbiter 32.
Typically, as the peripheral apparatus 33 intends to read data, the functional circuit 34 sends a request signal to the arbiter 32 to make a request. If the arbiter 32 grants the request of the functional circuit 34, the arbiter 32 of the multi-function master sends a request signal to the PCI bus 40 to request a use of the PCI bus 40. If the PCI bus 40 is not used by the other PCI master, the bus arbiter 31 sends a grant signal to the multi-function master 30 to give its privilege to use the PCI bus 40. Then, functional circuit 34 can send its request signal to the PCI bus 40 through the arbiter 32 and wait for data response. At this moment, if the other functional circuits 36, 38 or the peripheral apparatus 42 do also intend to use the PCI bus 40, they are sequentially authorized and wait until the previous action finishes.
When the data requested by the functional circuit 34 are ready, the functional circuit 34 starts to receive data from the PCI data bus 40 and transmit the data to its peripheral apparatus 33. The PCI bus 40 therefore is occupied by the functional circuit 34. In FIG. 3 and FIG. 4, when the functional circuit 34 is granted to use the PCI bus 40 at the time A, a period of time TA of the PCI bus is occupied by the functional circuit 34. In this period of time TA, an actual data transaction only uses a time of period TA1, which is about a half of the TA, resulting in a time consumption.
After the functional circuit 34 has completely received the desired data, the PCI bus 40 is still occupied by the multi-function master 30 except the bus arbiter 31 stops its authorization to the multi-function master 30. In this situation, the arbiter 32 continuously and sequentially grants, for example, the functional circuit 38 and the peripheral apparatus 42 for their data acquisition. In FIG. 4, TB and TC respectively represent the time occupied by the functional circuit 38 and the peripheral apparatus 42. Similarly, both the TB and TC use only about a half time for actual data transaction. After all requests of the multi-function master 30 has finished its data transaction, the multi-function master 30 then release its privilege on the PCI bus 40. The other PCI master then can use the PCI bus 40.
In the above operation example, the functional circuits 34 and 38 and the peripheral apparatus 42 use a total time T on the PCI bus 40. In this totally used active time T of the PCI bus 40, about a half of the active time is consumed without any action. The data transaction efficiency therefore is about 50% only. This is an inefficient performance.
Moreover, a current target device on the PCI bus 40, particularly like a host bridge, which includes the arbiter 31, usually has a multi-delay function. According to the conventional operation described above, the active time of the PCI bus 40 is greatly expended, and each of the functional circuits 34, 36, 38 and the peripheral apparatus 42 should sequentially acquire their desired data. A data transaction may be very simple further degrades the integrated performance of the PCI system. It is really necessary to modify the arbiter 32 of the multi-function master 30 and its arbitrating algorithm.
It is at least an objective of the present invention to provide a PCI bus master and its arbiter with an arbitrating method so as to reduce an occupation time on a PCI bus. The use efficiency of the PCI bus is improved.
It is at least another an objective of the present invention to provide a PCI bus master and its arbiter with an arbitrating method so as to allow several requests to use the PCI bus to be simultaneously sent to the PCI bus for preparation of various types of data. All the desired data having been prepared to be ready for acquisition have privilege to use the PCI bus. There is no need to sequentially wait for the necessary privilege. As a result, a delay time is averaged down so that the integrated performance is efficiently improved.
In accordance with the foregoing and other objectives of the present invention, a PCI bus master and its arbiter with an arbitrating method is provided. The PCI master includes at least one functional circuit and an arbiter. The functional circuit send a local inquiry signal to the arbiter to request a use of the PCI bus. The arbiter includes a rotating inquiry scheduler (RIS) and a heuristic inquiry initiator (HII). The RIS receives the local inquiry signal from the functional circuit and stores it. According to the local inquiry signal, a bus inquiry signal is generated and sent to the HII, and is sent to the PCI bus to request a use of the PCI bus. If the PCI bus responds a delay transaction termination, the HII can repeatedly send the bus inquiry signal to the PCI bus until the PCI bus grants the privilege to use the PCI bus. The HII then informs the RIS, which arranges the functional circuit to transmit data through the PCI bus.
In the foregoing, the RIS at least includes an inquiry queue and a response queue. As the RIS receives the local inquiry signal from the functional circuit, the RIS stores the local inquiry signal to the inquiry queue. Then, the RIS generates the bus inquiry signal, according to the local inquiry signal, and send the bus inquiry signal to the HII. The HII, according to the bus inquiry signal, obtains a privilege from the PCI bus. When the bus inquiry signal is sent to the PCI bus, the RIS then removes the local inquiry signal stored in the inquiry queue and alternatively stores the local inquiry signal to the response queue. As the PCI bus response is not the delay transaction termination, the RIS, according to the local inquiry signal stored in the response queue, setups a data transmission route to allow the functional circuit to transmit data through the PCI bus. The RIS also clears the local inquiry signal stored in the response queue after that.
The HII described above at least includes a buffer circuit, a register, and a time counter, in which the buffer circuit is coupled to the RIS. The buffer circuit also receives and temporarily stores the bus inquiry signal. According to the bus inquiry signal, the HII sends a PCI bus inquiry signal to the PCI bus. The time counter, which is coupled to the buffer circuit and the register, informs the buffer circuit, according to a delay time, or called a latency, stored in the register. The buffer circuit therefore repeatedly sends the bus inquiry signal to the PCI bus for continuous inquiry. The buffer circuit further includes an address cache memory and an adder. The address cache memory can fast access the address information carried by the bus inquiry signal. The adder, according to the address information carried by the bus inquiry signal or the received bus inquiry signal from the RIS, sends the PCI bus inquiry signal to the PCI bus.
The HII can include, for example, several HII units, each of which respectively includes a buffer circuit, a register, and a time counter with the coupling structure described above so that the HII can simultaneously process several bus inquiry signals. Moreover, the HII further includes a HII adder, which is coupled to the buffer of each HII unit. The HII adder sequentially sends the PCI bus inquiry signals to the PCI bus, according to the inquiry signals.
Moreover, a method for the HII to set each delay time of the inquiry signals includes initializing each delay time equal to a presetting delay time. The time counter informs each buffer circuit to re-send each of the PCI bus inquiry signals. If the PCI bus response is not a delay transaction termination and its responded delay time is greater than the presetting delay time, a delay decrement is subtracted from the current delay time so as to obtain a next delay time. If the second PCI bus response is a delay transaction termination, the current delay time is added with a delay increment to obtain the next delay time, which becomes the delay time for the next inquiry. The delay time is continuously adjusted until the desired data are transmitted.
In order to achieve the foregoing and other objectives of the present invention, an arbitrating method used for a compatible PCI bus master is provided. The arbitrating method provides several functional circuits respectively issuing several local inquiry signals to request a use of the PCI bus. The local inquiry signals are sequentially stored, and several PCI bus inquiry signals are accordingly produced and sent to the PCI bus. As a PCI bus response is a delay transaction termination, the same PCI bus inquiry signal corresponding to the one that gets the delay transaction termination is repeatedly sent to the PCI bus until the PCI bus response is not the delay transaction termination. As the PCI bus response is not the delay transaction termination, a granted functional circuit starts to fetch data through the PCI bus.
The arbitrating method used for a compatible PCI bus master further includes several steps. A delay time is provided. After the PCI bus responds a delay transaction termination, a waiting time starts to be counted. As the waiting time equals to the delay time, the same PCI bus inquiry is re-sent to the PCI bus. An initial delay time is first provided by setting it to a presetting delay time. The initial delay time is adjusted after each time of inquiry. If the PCI bus response of a second inquiry is not a delay transaction termination, a current delay time is greater than an actual delay responded from the target device, a new delay time is set by subtracting a delay decrement from the previous delay time. If the PCI bus response of the second inquiry is a delay transaction termination, a new delay time is set by adding a delay increment to the previous delay time. These subtracting and adding processes are continuously performed until the desired data is able to be transmitted.
Thin invention provides a compatible PCI bus master and its arbitrating method, in which the PCI bus master includes several arbiters so as to simultaneously process several PCI bus inquiry signals, which are repeatedly sent to the PCI bus. In this manner for the PCI bus master with multi-function capability, once the transaction data are ready, they have a chance to use the PCI. As a result, the PCI bus is more efficiently used by the multiple functional circuits, the active time is effectively increased, and the averaged delay time for each functional circuit is effectively reduced.